A field programmable gate array (FPGA) comprises an array of programmable logic blocks which can be programmably interconnected to each other to provide a logic function desired by a user. U.S. Pat. No. 4,870,302, reissued as U.S. Patent Re34,363 to Ross Freeman describes the first FPGA, and is incorporated herein by reference. Later patents such as U.S. Pat. No. 4,758,745 to Elgamal, and U.S. Pat. No. 5,243,238 to Kean, and published application WO 93/05577 invented by Furtek and owned by Concurrent Logic, Inc. describe other FPGA architectures. These patents and application are also incorporated herein by reference. The Xilinx 1994 Data Book entitled "The Programmable Logic Data Book", available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124 describes several FPGA products. As illustrated in the Xilinx data book, for example at page 2-114, FPGA products typically include a regular array of logic blocks, the number of which varies from one product to another.
An FPGA architecture includes a programmable routing structure and an array of configurable logic blocks. The programmable routing matrix includes means for connecting logic blocks to each other. Thus an FPGA provides a combination of programmable logic and programmable connections to a general routing structure.
In a typical FPGA application, the PIPs are turned on ahead of time by loading appropriate values into configuration memory cells associated with the PIPs, thus creating paths and establishing the logic performed by the configurable logic blocks. During operation, signals on the paths change dynamically as values are being written to and read from flip flops.
Some users need blocks of random access memory (RAM), for example so that complex functions generated in one part of the FPGA chip can be synchronized with complex logic generated in another part of the chip. For another example, users may want to provide a FIFO (first-in-first-out register) for buffering high speed data onto and off the chip, or to provide register banks for use by other logic in the chip.
In conventional FPGA chips these blocks of RAM are generated by configuring programmable parts of the FPGA, thus making these parts of the FPGA unavailable for other uses. When a common function such as PAM is desired by many users, it becomes economical to dedicate a portion of the chip to this purpose, thus allowing the particular function to be implemented at high density and leaving other parts of the FPGA free for less predictable uses.
The Altera FLEX 10K chip includes blocks of RAM that can be accessed by logic blocks in the chip. The Altera FLEX 10K structure is described briefly in a product information bulletin from Altera Corp. dated January 1996 and entitled "Benefits of Embedded RAM in FLEX 10K Devices". A block diagram on this publication shows a RAM/ROM block with several configurations. The RAM/ROM block is in an EAB (embedded array block) that includes input flip flops, a write pulse circuit, and input multiplexers for generating data, address, and write-enable signals from data, address, write enable, and input clock signals. The EAB also includes data-out flip flops and multiplexers for generating data-out signals. The Altera publication indicates that when large RAMs are desired, EABs are cascaded to implement larger RAMs.
However, these dedicated RAM blocks are accessed through general interconnect lines, and using general interconnect lines to access RAM decreases the availability of general interconnect lines for routing other logic signals.